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ez-pd? ccg2 datasheet usb type-c port controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-93912 rev. *l revised august 2, 2016 usb type-c port controller general description ez-pd? ccg2 is a usb type-c controller t hat complies with the latest usb type-c and pd standards. ez-pd ccg2 provides a complete usb type-c and usb power delivery port control soluti on for passive cables, active cables, and powered accessories. it can also be used in many upstream and downstream facing port applications. ez-pd ccg2 uses cypress?s proprietary m0s8 technology with a 32-bit, 48-mhz arm ? cortex ? -m0 processor with 32-kb flash and integrates a complete type-c transceiver including the type-c termination resistors r p , r d and r a . applications usb type-c emca cables usb type-c powered accessories usb type-c upstream facing ports usb type-c downstream facing ports features 32-bit mcu subsystem 48-mhz arm cortex-m0 cpu 32-kb flash 4-kb sram in-system reprogrammable integrated digital blocks integrated timers and counters to meet response times required by the usb-pd protocol run-time reconfigurable serial communication block (scb) with reconfigurable i 2 c, spi, or uart functionality clocks and oscillators integrated oscillator eliminating the need for external clock type-c support integrated transceiver (baseband phy) integrated ufp (r d ), emca (r a ) termination resistors, and current sources for dfp (r p ) supports one usb type-c port low-power operation 2.7-v to 5.5-v operation two independent vconn rails with integrated isolation between the two independent supply voltage pin for gpio that allows 1.71-v to 5.5-v signaling on the i/os reset: 1.0 a, deep sleep: 2.5 a, sleep: 2.0 ma system-level esd on cc and vconn pins 8-kv contact discharge and 15-kv air gap discharge based on iec61000-4-2 level 4c packages 1.63 mm 2.03 mm, 20-ball wafer-level csp (wlcsp) with 0.4-mm ball pitch 2.5 mm 3.5 mm 0.6 mm 14-pin dfn 4.0 mm 4.0 mm, 0.55 mm 24-pin qfn supports industrial ( ? 40 c to +85 c) and extended industrial ( ? 40 c to +105 c) temperature ranges logic block diagram flash (32 kb) sram (4 kb) serial wire debug programmable io matrix ccg2: usb type-c cable controller cortex-m0 48 mhz integrated digital blocks i/o subsystem mcu subsystem advanced high-per formance bus (ahb) cc 5 gpio 6 port 1 timer, counter, pulse-width modulation block 2 serial communication block configurable as uart, spi, or i 2 c 3 termination resistor denoting a ufp 4 termination resistor denoting an emca 5 configuration channel 6 general-purpose input/output 7 current sources to indicate a dfp profiles and configurations baseband mac baseband phy scb 2 (i 2 c, spi, uart) integrated r d 3 , r a 4 , and r p 7 vconn1 vconn2 vddio tcpwm 1 scb 2 (i 2 c, spi, uart)
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 2 of 33 available firmware and software tools ez-pd configuration utility the ez-pd configuration ut ility is a gui-based microsoft windows application developed by cypress to guide a ccgx user through the process of configuring and programming the chip. the utility allows users to: 1. select and configure the parameters they want to modify 2. program the resulting configurat ion onto the target ccgx device. the utility works with the cypress supplied ccg1, ccg2, ccg3, an d ccg4 kits, which host the ccgx controllers along with a usb interface. this version of the ez-pd conf iguration utility supports configuration and firmware update operations on ccgx contro llers implementing emca and display dongle applications. support for other applications, such as po wer adapters and notebook port controllers, will be provided in later versions of the utility. you can download the ez-pd configur ation utility and its associated do cumentation at the following link: http://www.cypress.com/ documentation/software-and-drivers/ez-pd-configuration-utility
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 3 of 33 contents functional overview .........................................................4 cpu and memory subsystem .....................................4 usb-pd subsystem (ss) ....... .............. .............. .........5 system resources .......................................................5 peripherals ..................................................................6 gpio ............................................................................6 pinouts ...............................................................................7 power .................................................................................9 application diagrams .....................................................10 electrical specifications .................................................17 absolute maximum ratings .... ...................................17 device level specifications .......................................18 digital peripherals ......................................................20 memory ......................................................................22 system resources .....................................................23 ordering information ......................................................26 ordering code definitions .........................................26 packaging ........................................................................27 acronyms ........................................................................29 document conventions .................................................30 units of measure .......................................................30 references and links to applications collaterals ....31 document history page .................................................32 sales, solutions, and legal information ......................33 worldwide sales and design support ...... ............ .....33 products ....................................................................33 psoc? solutions ................... ....................................33 cypress developer community .................................33 technical support ............... .......................................33
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 4 of 33 figure 1. ez-pd ccg2 block diagram functional overview cpu and memory subsystem cpu the cortex-m0 cpu in ez-pd ccg 2 is part of the 32-bit mcu subsystem, which is optimized for low-power operation with extensive clock gating. it mostly uses 16-bit instructions and executes a subset of the thumb- 2 instruction set. this enables fully compatible binary upward migration of the code to higher performance processors such as the cortex-m3 and m4, thus enabling upward compatibility. the cypress implementation includes a hardware multiplier that provides a 32-bit result in one cycle. it includes a nested vector ed interrupt controller (nvic) block with 32 interrupt inputs and also includes a wakeup interrupt controller (wic). the wic can wake the processor up from the deep sleep mode, allowing power to be switched off to the main processor when the chip is in the deep sleep mode. the cortex-m0 cpu provides a non-maskable interrupt (nmi) input, which is made available to the user when it is not in use for system functions requested by the user. the cpu also includes a serial wire debug (swd) interface, which is a 2-wire form of jtag. the debug configuration used for ez-pd ccg2 has four break-point (address) comparators and two watchpoint (data) comparators. flash the ez-pd ccg2 device has a flash module with a flash accelerator, tightly coupled to the cpu to improve average access times from the flash block. the flash block is designed to deliver 1 wait-state (ws) access time at 48 mhz and with 0-ws access time at 24 mhz. the flash accelerator delivers 85% of single-cycle sram access performance on average. part of the flash module can be used to emulate eeprom operation if required. srom a supervisory rom that contains boot and configuration routines is provided. ccg2 32-bit ahb-lite cpu subsystem sram 4 kb sram controller srom 8 kb srom controller flash 32 kb read accelerator spcif deep sleep active/sleep swd/tc nvic, irqmx cortex m0 48 mhz fast mul system interconnect (single layer ahb) i/o subsystem 12 x gpios, 2 x ovts ioss gpio (3 x ports) peripherals peripheral interconnect (mmio) pclk high speed i/o matrix usb-pd ss cc bb phy power modes 6 x tcpwm dft logic test dft analog system resources lite power clock wdt ilo reset clock control imo sleep control pwrsys ref por wic reset control xres 2 x vconn pads, esd 2 x scb
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 5 of 33 usb-pd subsystem (ss) ez-pd ccg2 has a usb-pd s ubsystem consisting of a usb type-c baseband transceiver and physical-layer logic. this transceiver performs the bmc and the 4b/5b encoding and decoding functions as well as the 1.2-v front end. this subsystem integrates the requir ed termination resistors to identify the role of t he ez-pd ccg2 solution. r a is used to identify ez-pd ccg2 as an accessory or an electronically marked cable. r d is used to identify ez-pd ccg2 as a ufp in a hybrid cable or a dongle. when configured as a dfp, integrated current sources perf orm the role of r p or pull-up resistors. these current sources can be programme d to indicate the complete range of current capacity on vbus defined in the type-c spec. ez-pd ccg2 responds to all usb-pd communication. the ez-pd ccg2 usb-pd sub-system can be configured to respond to sop, sop', or sop? messaging. the usb-pd sub-system contai ns a 8-bit sar (successive approximation register) adc for an alog to digital conversions. the adc includes a 8-bit dac and a comparator. the dac output forms the positive input of the comparator. the negative input of the comparator is from a 4-input multiplexer. the four inputs of the multiplexer are a pair of global analog multiplex busses an internal bandgap voltage and an internal voltage proportional to the absolute temper ature. all gpio inputs can be connected to the global analog multiplex busses through a switch at each gpio that can en able that gpio to be connected to the mux bus for adc use. the cc1, cc2 and rd1 pins are not available to connect to the mux busses. figure 2. usb-pd subsystem system resources power system the power system is described in detail in the section power on page 9 . it provides assurance that voltage levels are as required for each respective mode and either delay mode entry (on power-on reset (por), for example) until voltage levels are as required for proper function or generate resets (brown-out detect (bod)) or interrupts (low voltage detect (lvd)). ez-pd ccg2 can operate from three different power sources over the range of 2.7 to 5.5 v and has three different power modes, transitions between which are managed by t he power system. ez-pd ccg2 provides sleep and deep sleep low-power modes. clock system the clock system for ez-pd ccg2 co nsists of the internal main oscillator (imo) and the inter nal low-power oscillator (ilo). 4b5b encoder sop detect crc 4b5b decoder tx_data from ahb rx_data to ahb to/ from ahb vref iref vddd to/from system resources sop insert 8-bit adc from amux cc detect vconn2 detect vconn1 detect tx rx cc2 cc1 ref 8kv iec esd vconn detect ra ra enable logic 8kv iec esd active rd rp rd1 db rd comp ra enable cc control enable logic txrx enable bmc decoder bmc encoder digital baseband phy analog baseband phy vconn power logic vconn2 vconn1 deep sleep vref & iref gen vref, iref tx sram rx sram deep sleep reference enable functional, wakeup interrupts vddd
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 6 of 33 peripherals serial communication blocks (scb) ez-pd ccg2 has two scbs, which can be configured to implement an i 2 c, spi, or uart interface. the hardware i 2 c blocks implement full multi-master and slave interfaces capable of multimaster arbitration. in the spi mode, the scb blocks can be configured to act as master or slave. in the i 2 c mode, the scb blocks are capable of operating at speeds of up to 1 mbps (fast mode plus) and have flexible buffering options to reduce interrupt overhead and latency for the cpu. these blocks also support i 2 c that creates a mailbox address range in the memory of ez-pd ccg2 and effectively reduce i 2 c communication to reading from and writing to an array in memory. in addition, the blocks support 8-deep fifos for receive and transmit which, by increasing the time given for the cpu to read data, greatly reduce the need for clock stretching caused by the cpu not having read data on time. the i 2 c peripherals are compatible with the i 2 c standard-mode, fast-mode, and fast-mode plus devices as defined in the nxp i 2 c-bus specification and user manual ( um10204 ). the i 2 c bus i/os are implemented with gp io in open-drain modes. the i 2 c port on scb 1 block of ez-pd ccg2 is not completely compliant with the i 2 c spec in the following respects: the gpio cells for scb 1's i 2 c port are not overvoltage-tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the i 2 c system. fast-mode plus has an i ol specification of 20 ma at a v ol of 0.4 v. the gpio cells can sink a maximum of 8-ma i ol with a v ol maximum of 0.6 v. fast-mode and fast-mode plus specify minimum fall times, which are not met with the gpio cell; slow strong mode can help meet this spec depending on the bus load. timer/counter/pwm block (tcpwm) ez-pd ccg2 has six tcpwm blocks. each implements a 16-bit timer, counter, pulse-width modulator (pwm), and quadrature decoder functionality. the block can be used to measure the period and pulse width of an input signal (timer), find the number of times a particular event occurs (counter), generate pwm signals, or decode quadrature signals. gpio ez-pd ccg2 has up to 10 gpios in addition to the i 2 c and swd pins, which can also be used as gpios. the i 2 c pins from scb 0 are overvoltage-tolerant. the nu mber of available gpios vary with the package. the gpio block implements the following: seven drive strength modes: ? input only ? weak pull-up with strong pull-down ? strong pull-up with weak pull-down ? open drain with strong pull-down ? open drain with strong pull-up ? strong pull-up with strong pull-down ? weak pull-up with weak pull-down input threshold select (cmos or lvttl) individual control of input and output buffer enabling/disabling in addition to the drive strength modes hold mode for latching previous state (used for retaining i/o state in deep sleep mode) selectable slew rates for dv/dt related noise control to improve emi during power-on and reset, the i/o pins are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. a multiplexing network known as a high-speed i/o matrix is used to multiplex between various signals that may connect to an i/o pin.
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 7 of 33 pinouts group name pin map 24-qfn ball location 20-csp pin map 14-dfn description usb type-c port cc1 2 b4 3 usb pd connector detect/configuration channel 1 cc2 1 a4 n/a usb pd connector detect/configuration channel 2 rd1 3 b3 n/a dedicated rd resistor pin for cc1 must be left open for cable applications and connected together with cc1 ball for ufp or dfp with dead battery applications gpios and serial interfaces gpio 22 c3 n/a gpio / spi_0_clk / uart_0_ rx gpio 18 d3 13 gpio / spi_0_mosi / uart_0_tx gpio 13 c2 10 gpio / i2c_1_sda / spi_1_miso / uart_1_rx gpio 10 d2 n/a gpio / i2c_1_scl / spi_1_clk / uart_1_tx gpio 15 b2 11 gpio / spi_1_sel / uart_1_rts gpio 14 n/a n/a gpio gpio 17 n/a n/a gpio gpio 21 n/a n/a gpio gpio 23 n/a n/a gpio gpio 24 n/a n/a gpio i2c_0_scl 20 a3 1 gpio / i2c_0_scl / spi_0_miso / uart_0_rts i2c_0_sda 19 a2 14 gpio / i2c_0_sda / spi_0_sel / uart_0_cts swd _io 11 e2 8 swd io / gpio / uart_1_cts / spi_1_mosi swd_clk 12 d1 9 swd clock / gpio reset xres 16 b1 12 reset input power vconn1 5 e4 5 vconn 1 input (4.0 v to 5.5 v) vconn2 4 c4 4 vconn 2 input (4.0 v to 5.5 v) vddio 8 e1 n/a 1.71-v to 5.5-v supply for i/os vccd 7 a1 6 1.8-v regulator output for filter capacitor vddd 9 e3 7 vddd supply input/output (2.7 v to 5.5 v) vddd 6 vddd supply input/output (2.7 v to 5.5 v) vss epad n/a epad ground supply vss d4 2 ground supply vss c1 ground supply
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 8 of 33 figure 3. 20-ball wlcsp ez-pd ccg2 ball map (bottom (balls up) view) figure 4. 14-pin dfn pin map (top view) figure 5. 24-pin qfn pin map (top view) 4321 a b c d cc2 cc1 vconn2 vss i2c_0_sda gpio i2c_0_scl rd1 gpio gpio gpio gpio vccd xres vss swd_clk e vconn1 swd_io vddd vddio 14 13 12 11 10 9 8 1 2 3 4 5 6 7 i2c_0_sda gpio xres gpio gpio swd_clk swd_io i2c_0_scl vss cc1 vconn2 vconn1 vccd vddd 1 2 3 4 5 6 cc2 cc1 rd1 vconn2 vconn1 vddd 7 8 9 10 11 12 vccd vddio vddd gpio swd_io swd_clk 18 17 16 15 14 13 gpio gpio xres gpio gpio gpio 24 23 22 21 20 19 gpio gpio gpio gpio i2c_0_scl i2c_0_sda epad
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 9 of 33 power the following power system diagr am shows the set of power supply pins as implemented in ez-pd ccg2. ez-pd ccg2 can operate from three different power sources. vconn1 and vconn2 pins can be used as connections to the vconn pins on a type-c plug of a cable or vconn-powered accessory. each of these inputs support operation over 4.0 to 5.5 v. an internal isolation between vconn1 and vconn2 pins is provided allowing them to be at different levels simultaneously. ccg2 can be used in emca applications with only one or both vconn pins as power sources. this is illustrated later in the section on applications. besides being power inputs, each vconn pin is also internally connected to a r a termination resistor required for emca and vconn-powered accessories. ez-pd ccg2 can also be operate from 2.7 to 5.5 v when operated from the vddd supply pin. vconn-powered accessory applications require that ccg2 work down to 2.7 v. in such applications, both the vddd and vconn pins should be connected to the vconn pin of the type-c plug in the accessory. in ufp, dfp, and drp applications, ccg2 can be operated from vddd as the only supply input. in such applications, the vconn pins are left open. in dfp applications, the lowest vddd level that ccg2 can operate is 3.0 v due to the need to support disconnect detection thresholds of up to 2.7 v. a separate i/o supply pin, vddi o, allows the gpios to operate at levels from 1.71 to 5.5 v. the vddio pin can be equal to or less than the voltages connec ted to the vconn1, vconn2, and vddd pins. the independent vddio supply is not available on the 14-dfn package. on this package, the vddio rail is internally connected to the vddd rails. the vccd output of ez-pd ccg2 must be bypassed to ground via an external capacitor (in the range of 1 to 1.6 f; x5r ceramic or better). bypass capacitors must be used from vddd and vconn pins to ground; typical practice for systems in this frequency range is to use a 0.1-f capacitor. note that these are simply rules of thumb and that for critical app lications, the pcb layout, lead inductance, and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing. an example of the power supply bypass capacitors is shown in figure 6 . figure 6. ez-pd ccg2 power and bypass scheme example r a v ss v conn2 v ddd core regulator (srsslt) v conn1 v ccd core v ddio gpio cc tx/rx r a 1uf 1uf 0.1uf 0.1uf
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 10 of 33 application diagrams figure 7 and figure 8 show the application diagrams of a passive emca application using ccg2 devices. figure 7 shows the application using a single ccg 2 device per cable present at one of the two plugs, whereas figure 8 shows the same with two ccg2 devices per cable present at each plug. the vbus signal, the superspeed lines, highspeed lines, and cc lines are connected directly from one end to another. the application diagram shown in figure 7 requires a single vconn wire to run through the cable so that the ccg2 device can be powered irrespective of which plug is connected to the host (dfp). however, in the application diagram shown in figure 8 , the vconn signal does not run through the entire cable, but only runs to the respective vconn pin of the ccg2 device at each end of the plug . also, only one ccg2 device is powered at any given instance, depending on which one is nearer to the dfp that supplies vconn. figure 7. passive emca application ? single ez-pd ccg2 per cable vconn 1 vbus cc type-c plug gnd type-c plug vconn 2 superspeed and highspeed lines 0.1uf ccg2 vddd e3 1uf a1 vccd vss c1 xres b1 swd_ io swd_ clk e2 d1 i2c_0 _scl i2c_0 _sda a3 a2 b4 cc1 gpio gpio d3 c2 cc2 a4 e4 vconn1 c4 vconn2 vddio e1 rd1 b3 vss d4 gpio d2 gpio b2 gpio c3 0.1uf 1uf vddio 4.7 k 20-csp
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 11 of 33 figure 8. passive emca applic ation ? single ez-pd ccg2 per plug figure 9 shows a ccg2 device being used in a ufp application (t ablet with a type-c port) only as a power consumer. the type-c receptacle brings in highspeed and superspeed lines, wh ich are connected directly to the applications processor. the vbus line from the type-c receptacle goes directly to the ufp (t ablet) charger circuitry. the applications processor communicat es over the i 2 c signal with the ccg2 device, and the cc1 and cc2 lines from the type-c receptacle are connected directly to the respective cc1/2 pins of the ccg2 device. figure 9. upstream facing port (ufp) application ? tablet with a type-c port vconn vbus cc type-c plug type-c plug vconn gnd superspeed and highspeed lines ccg2 vddd e3 1uf a1 vccd vss c1 xres b1 swd_ io swd_ clk e2 d1 i2c_0 _scl i2c_0 _sda a3 a2 b4 cc1 gpio gpio d3 c2 cc2 a4 e4 vconn1 c4 vconn2 vddio e1 1uf 0.1uf rd1 b3 vss d4 gpio d2 gpio b2 gpio c3 ccg2 vddd e3 1uf a1 vccd vss c1 xres b1 swd_ io swd_ clk e2 d1 i2c_0 _scl i2c_0 _sda a3 a2 b4 cc1 gpio gpio d3 c2 cc2 a4 c4 vconn2 e4 vconn1 vddio e1 1uf 0.1uf rd1 b3 vss d4 gpio d2 gpio b2 gpio c3 vddio vddio 4.7k 4.7k vbus application processor type-c receptacle highspeed lines ccg2 vddd e3 i2c_0_sda a2 gpio c3 vccd xres a1 b1 vss vss d4 c1 b4 cc1 gpio gpio d3 c2 cc2 a4 e4 vconn1 vddio e1 1uf rd1 b3 i2c_0_scl a3 gpio d2 gpio b2 swd_io e2 1uf swd_clk d1 c4 vconn2 1uf 5.0 v 1.8 v charger application processor/ graphics controller superspeed lines 1.8 v int 1.8 v 4.7 k 4.7 k 4.7 k 390 pf 390 pf
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 12 of 33 figure 10 shows a notebook drp application diagram using a ccg2 device. the type-c port can be used as a power provider or a power consumer. the ccg2 device communicates with the embedded controller (ec) over i 2 c. it also controls the data mux to route the high speed signals either to the usb chipset (during normal mode) or the displayport chipset (during alternate mode). the sbu lines, superspeed and highspeed lines are routed directly from the display mux of the notebook to the type-c receptacle. optional fets are provided for applications that need to provide power for accessories and cables using the vconn pin of the type-c receptacle. vbus fets are also used for providing power over vbus and for consuming power over vbus. a vbus_discharge fet controlled by ccg2 device is used to quickly discharge vbus after the type-c connection is detached. figure 10. dual role port (drp) application ccg2 24-qfn vddd vddd vddio vccd 6 9 8 7 gpio gpio gpio 13 10 23 gpio 15 gpio 18 gpio 22 gpio 21 gpio 24 cc2 1 cc1 2 rd1 3 vconn1 5 vconn2 4 swd_io 11 swd_clk 12 gpio 14 i2c_0_scl 20 i2c_0_sda 19 xres 16 vss epad 1uf 3.3v vddio vddio 1uf vbus_p_ctrl vbus_discharge vbus_c_ctrl type-c receptacle vbus (5-20v) vddio i2c_int vbus_sink vbus_source 5.0v 5.0v optional fets for dfps supporting vconn vbus fets for consumer path cc1_vconn_ctrl cc2_vconn_ctrl vbus_discharge vbus_c_ctrl vbus_p_ctrl hpd usb chipset embedded controller hpd dc/dc charger gpio 17 vbus vbus_mon 390pf 390pf vbus fets for provider path 100k 10k 2.2k 2.2k 2.2k 4.7k d+/- ss displayport chipset data mux dp0/1/2/3 aux+/- scl sda gnd ss hs/ss/dp/ sbu lines dp/dn d+/- ss cc1 cc2 vbus
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 13 of 33 figure 11 shows a ccg2 receptacle-based power adapter application in which the ccg2 device is used as a dfp. ccg2 integrates all termination resistors and uses gpios (vsel_0 and vsel_1) to indicate the negotiated power profile. the vbus voltage on the type-c port is monitored using internal adc to detect undervoltage and overvoltage conditions on vbus. to ensure quick discharge of vbus when the power adapter cable is detached, a discharge path is also provided. figure 11. downstream facing port (dfp) application ccg2 24-qfn vddd vddd vddio vccd 6 9 8 7 gpio gpio gpio 13 10 23 gpio 15 gpio 18 gpio 22 gpio 21 gpio 24 cc2 1 cc1 2 rd1 3 vconn1 5 vconn2 4 swd_io 11 swd_clk 12 gpio 14 gpio 20 gpio 19 xres 16 vss epad 1uf 3.3v vddio vddio 1uf vbus_p_ctrl vbus_discharge type-c receptacle vbus (5-20v) vbus_in 5.0v 5.0v optional fets for dfps supporting vconn cc1_vconn_ctrl cc2_vconn_ctrl vbus_discharge vbus_p_ctrl dc/dc or ac-dc secondary (5-20v) gpio 17 vbus vbus_mon optional vddio supply. can short to vddd in single supply systems vsel_1 and vsel_0 control the secondary side of an ac-dc or a dc-dc to select the voltage on vbus_in. an example is shown below: vsel_1 vsel_0 vsel_1 vsel_0 390pf 390pf 100k 10k 4.7k vsel_1 vsel_0 vbus_in 005v 019v 1015v 1120v
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 14 of 33 figure 12 shows a usb type-c to hdmi/dvi/vga adapter appli- cation, which enables connectivity between a pc that supports a type-c port with displayport alternate mode support and a legacy monitor that has hdmi/dvi/vga interface. it enables users of any notebook that im plements usb-type c to connect to other display types. this application has a type-c plug on one end and the legacy video (hdmi/dvi/vga) receptacle on the other end. this appli- cation meets the requirements de scribed in section 4.3 of the vesa displayport alt mode on usb type-c standard version 1.0. this application supports di splay output at a resolution of up to 4k ultra hd (3840x2160) at 60 hz. it also supports the usb billboard device class, which is required by the usb pd speci- fication for enumeration of any accessories that support alternate mode when connected to a host pc. figure 12. usb type-c to hdmi/dv i/vga dongle application diagram type-c plug usb-billboard cy7c65210 hdmi/dvi/ vga receptacle power or vbus vconn vbus d+/- cc sw for aux sbu_1/2 hotplug detect 2.2k 5% 2.2k 5% scl sda xres int 3.3v cypd2119 24qfn cc1 rd1 cc2 2 3 1 epad vccd 7 p1.7 p2.1 p1.3 p1.0 18 10 13 22 vddd1 vddd2 vddio vconn1 5 6 9 8 vconn2 p1.6 4 17 xres 4.7k 16 p1.5 15 p2.3:p0.0 p0.1 1 f p1.4 vconn 3.3v 1 f 100k ,1% 10k ,1% vbus p2.0 p2.2 swd_clk swd_io 12 11 21 23 [24:19] 20 14 buckboost 5v regulator 3.3v 1.2v dp to hdmi/ dvi/vga convertor 3.3v 1.2v display port data lanes 2.2k 5% vbus_vconn vbus_vconn 1 f 0.1 f
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 15 of 33 figure 13 shows a usb type-c to displayport adapter appli- cation, which enables connectivity between a pc that supports a type-c port with displayport alternate mode support and a legacy monitor that has a displayport interface. figure 13 shows a type-c plug on one end and a dp/mdp plug on the other end. the application meets the requirements described in section 4.2 of t he vesa displayport alt mode on usb type-c standard version 1.0 (scenarios 2a and 2b usb type-c to displayport cables). it also supports the usb billboard device class, which is required by the usb pd speci- fication for enumeration of any accessories that support alternate mode when connected to a host pc. figure 13. usb type-c to di splay port application diagram type-c plug usb-billboard cy7c65210 mdp/ dp power or vbus vconn vbus_vconn vbus d+/- cc display port data lanes sw for aux sbu_1/2 aux_p/n paddle card hotplug detect 2.2k 5% 2.2k 5% scl sda xres int vbus_vconn cypd2120 24qfn cc1 rd1 cc2 2 3 1 epad vccd 7 p1.7 p2.1 p1.3 p1.0 18 10 13 22 vddd1 vddd2 vddio vconn1 5 6 9 8 vconn2 p1.6 4 17 xres 4.7k 16 p1.5 15 p2.3:p0.0 p0.1 1 f p1.4 0.1 f vconn vbus_vconn 1 f 100k ,1% 10k ,1% vbus p2.0 p2.2 swd_clk swd_io 12 11 21 23 [24:19] 20 14 2.2k 5% display port data lanes
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 16 of 33 figure 14 shows a ccg2 monitor/dock application diagram. it enables connectivity between a usb type-c host system on the upstream port and multiple display/data devices on the downstream port. this application has a usb type-c receptacle on the upstream port, which supports data, po wer, and display. on the downstream port, this application supports: usb type-a , gigabit ethernet, displayport, and usb type-c receptacle. the main features of this solution are: powered from an external 24-v dc power adapter provides up to 45 w (15 v at 3a) on the upstream type-c port and up to 15 w (5 v at 3a) on the downstream usb type-c port provides simultaneous 4k display output with usb 3.1 gen 1 on the usb type-a port four-lane display on the displayport connector multi-stream support on displayport and downstream type-c port usb 3.1 gen 1 hub for usb port expansion gigabit ethernet using rj45 connector supports firmware upgrade of ccg2 controllers, hx3 hub controller, and billboard controller figure 14. ccg2 in dock/monitor application diagram type-c to notebook usb-billboard cy7c65210 vbus_us 5v cc1 sbu_1/2 hotplug detect 2.2k 5% 2.2k 5% scl sda int2 int1 3.3v drp cypd2121 24qfn cc1 rd1 cc2 2 3 1 epad vccd 7 p1.4 p0.0 p0.1 14 19 20 vddd1 vddd2 xres vddio 1 f 8 6 9 16 vconn2 p1.6 4 17 vconn1 4.7k 5 p2.1 12 swd_clk_p1.2 p2.2 p1.5 0.1 f 3.3v 1 f 100k ,1% 10k ,1% vbus swd_io_p1.1 11 23 15 5v 3.3v 1.2v type-c mux ss data lanes 2.2k 5% 100k 1k 100k regulator us_vbus_p_ctrl vsel_1 vsel_0 0.1 f us_vbus_dis 22 100 p1.3 p1.0 2.2k 5% 2.2k 5% 13 10 p1.7 p2.3 vsel_0 vsel_1 18 24 p2.0 21 hub_vbus_us cc2 sda scl hpd dp spliter dp port usb hub cyusb3304 -68ltxc hub_vbus_us ss data lines usb d+/- usb d+/- sys_i2c_sda sys_i2c_scl sys_i2c_scl sys_i2c_scl hs_ds2 hs_ds2 ds1 ds3 hs_ds4 usb type-a receptacle ethernet gx3 cyusb3610- 68ltxc ss_ds4 type-c to device vbus_ds vconn cc1 ds_hotplug detect 3.3v dfp cypd2125 24qfn rd1 cc1 cc2 3 2 1 epad vccd 7 p2.3 p2.1 p0.0 p0.1 24 22 19 20 vddd1 vddd2 xres vddio 1 f 8 6 9 16 vconn2 p1.6 4 17 vconn1 4.7k 5 p2.0 12 swd_clk p2.2 p1.5 0.1 f 3.3v 1 f 100k ,1% 10k ,1% vbus swd_io 11 23 15 type-c mux ss data lines_2 100k 1k 100k us_vbus_p_ctrl 0.1 f ds_vbus_dis 21 100k p1.3 p1.0 2.2k 5% 2.2k 5% 13 10 p1.7 18 cc2 sda scl hpd hs_ds4 sys_i2c_sda sys_i2c_scl 100k 200k vconn 100k 200k p1.4 ds_i2c_int 14 dp2 dp2 ss_ds4 ds_hotplug detect 5.0v power 5-20v 5-20v discharge nfet us_vbus_dis ss data lines_1 power in brick discharge nfet ds_vbus_dis ds_i2c_int i2c master i2c slave i2c master ccg2 connected on the upstream port ccg2 connected on the downstream port cypress usb3.0 hub
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 17 of 33 electrical specifications absolute maximum ratings table 1. absolute maximum ratings [1] parameter description min typ max units details/conditions v ddd_max digital supply relative to v ss ?0.5 ? 6 v absolute max v conn1_max max supply voltage relative to v ss ? ? 6 v absolute max v conn2_max max supply voltage relative to v ss ? ? 6 v absolute max v ddio_max max supply voltage relative to v ss ? ? 6 v absolute max v gpio_abs gpio voltage ?0.5 ? v ddio + 0.5 v absolute max v cc_abs absolute max voltage for cc1 and cc2 pins ? ? 6 v absolute max i gpio_abs maximum current per gpio ?25 ? 25 ma absolute max i gpio_injection gpio injection cu rrent, max for v ih > v ddd , and min for v il < v ss ?0.5 ? 0.5 ma absolute max, current injected per pin esd_hbm electrostatic discharge human body model 2200 ? ? v ? esd_cdm electrostatic discharge charged device model 500 ? ? v ? lu pin current for latch-up ?200 ? 200 ma ? esd_iec_con electrostatic discharge iec61000-4-2 8000 ? ? v contact discharge on cc1, cc2, vconn1, and vconn2 pins esd_iec_air electrostatic discharge iec61000-4-2 15000 ? ? v air discharge for pins cc1, cc2, vconn1, and vconn2 note 1. usage above the absolute maximum conditions listed in tab l e 1 may cause permanent damage to the device. expos ure to absolute maximum conditions for extended periods of time may affect device reliabilit y. the maximum storage temperature is 150 c in compliance with jedec standard jesd2 2-a103, high temperature storage life. when used below absolute maximum conditions but a bove normal operating conditions, the device may not operate to specification.
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 18 of 33 device level specifications all specifications are valid for ?40 c ? ta ? 85 c and tj ? 100 c, except where noted. specific ations are valid for 3.0 v to 5.5 v, except where noted. table 2. dc specifications spec id parameter description min typ max units details/conditions sid.pwr#1 v ddd power supply input voltage 2.7 ? 5.5 v ufp applications sid.pwr#1_a v ddd power supply input voltage 3.0 ? 5.5 v dfp/drp applications sid.pwr#23 v conn1 power supply input voltage 4.0 ? 5.5 v ? sid.pwr#23_a v conn2 power supply input voltage 4.0 ? 5.5 v ? sid.pwr#13 v ddio gpio power supply 1.71 ? 5.5 v ? sid.pwr#24 v ccd output voltage (for core logic) ? 1.8 ? v ? sid.pwr#15 c efc external regulator voltage bypass on v ccd 11.31.6 f x5r ceramic or better sid.pwr#16 c exc power supply decoupling capacitor on v ddd ?1 ? f x5r ceramic or better sid.pwr#25 power supply decoupling capacitor on v conn1 and v conn2 ?0.1 ? f x5r ceramic or better active mode, v ddd = 2.7 to 5.5 v. typical values measured at v dd = 3.3 v . sid.pwr#12 i dd12 supply current ? 7.5 ? ma v conn1 or v conn2 = 5 v, t a = 25 c, cc i/o in transmit or receive, r a disconnected, no i/o sourcing current, cpu at 12 mhz sleep mode, v ddd = 2.7 to 5.5 v sid25a i dd20a i 2 c wakeup. wdt on. imo at 48 mhz ?2.03.0ma v ddd = 3.3 v, t a = 25 c, all blocks except cpu are on, cc i/o on, no i/o sourcing current deep sleep mode, v ddd = 2.7 to 3.6 v (regulator on) sid_ds_ra i dd_ds_ra v conn1 = 5.0, r a termination disabled ? 100 ? a v conn1 , v conn2 = 5 v, t a = 25 c. r a termination disabled on v conn1 and v conn2 , see sid.pd.7. vconn leaker circuits turned off during deep sleep sid34 i dd29 v ddd = 2.7 to 3.6 v. i 2 c wakeup and wdt on ?50 ? a r a switch disabled on v conn1 and v conn2 . v ddd = 3.3 v, t a = 25 c sid_ds i dd_ds v ddd = 2.7 to 3.6 v. cc wakeup on ? 2.5 ? a power source = v ddd , type-c not attached, cc enabled for wakeup, r p disabled xres current sid307 i dd_xr supply current while xres asserted ? 1 10 a?
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 19 of 33 i/o table 3. ac specifications spec id parameter description min typ max units details/conditions sid.clk#4 f cpu cpu frequency dc ? 48 mhz 3.0 v ?? v ddd ?? 5.5 v sid.pwr#20 t sleep wakeup from sleep mode ? 0 ? s guaranteed by characterization sid.pwr#21 t deepsleep wakeup from deep sleep mode ? ? 35 s 24-mhz imo. guaranteed by charac- terization sid.xres#5 t xres external reset pulse width 5 ? ? s guaranteed by characterization sys.fes#1 t _pwr_rdy power-up to ?ready to accept i2c / cc command? ? 5 25 ms guaranteed by characterization table 4. i/o dc specifications spec id parameter description min typ max units details/conditions sid.gio#37 v ih [2] input voltage high threshold 0.7 v ddio ?? vcmos input sid.gio#38 v il input voltage low threshold ? ? 0.3 v ddio vcmos input sid.gio#39 v ih [2] lvttl input, v ddio < 2.7 v 0.7 v ddio ?? v ? sid.gio#40 v il lvttl input, v ddio < 2.7 v ? ? 0.3 v ddio v? sid.gio#41 v ih [2] lvttl input, v ddio ? 2.7 v 2.0 ? ? v ? sid.gio#42 v il lvttl input, v ddio ? 2.7 v ? ? 0.8 v ? sid.gio#33 v oh output voltage high level v ddio ? 0.6 ? ? v i oh = 4 ma at 3-v v ddio sid.gio#34 v oh output voltage high level v ddio ? 0.5 ? ? v i oh = 1 ma at 1.8-v v ddio sid.gio#35 v ol output voltage low level ? ? 0.6 v i ol = 4 ma at 1.8-v v ddio sid.gio#36 v ol output voltage low level ? ? 0.6 v i ol = 8ma at 3v v ddio sid.gio#5 r pullup pull-up resistor 3.5 5.6 8.5 k ? ? sid.gio#6 r pulldown pull-down resistor 3.5 5.6 8.5 k ? ? sid.gio#16 i il input leakage current (absolute value) ?? 2na 25 c, v ddio = 3.0 v.guaranteed by characterization sid.gio#17 c in input capacitance ? ? 7 pf guaranteed by characterization sid.gio#43 v hysttl input hysteresis lvttl 25 40 ? mv v ddio ? 2.7 v. guaranteed by characterization. sid.gpio#44 v hyscmos input hysteresis cmos 0.05 v ddio ??mv guaranteed by characterization sid69 i diode current through protection diode to v ddio /vss ? ? 100 a guaranteed by characterization sid.gio#45 i tot_gpio maximum total source or sink chip current ? ? 200 ma guaranteed by characterization note 2. v ih must not exceed v ddio + 0.2 v.
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 20 of 33 xres digital peripherals the following specifications apply to the time r/counter/pwm peripheral s in the timer mode. pulse width modulation (pwm) for gpio pins table 5. i/o ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid70 t risef rise time 2 ? 12 ns 3.3-v v ddio , cload = 25 pf sid71 t fallf fall time 2 ? 12 ns 3.3-v v ddio , cload = 25 pf table 6. xres dc specifications spec id parameter description min typ max units details/conditions sid.xres#1 v ih input voltage high threshold 0.7 v ddio ??vcmos input sid.xres#2 v il input voltage low threshold ? ? 0.3 v ddio vcmos input sid.xres#3 c in input capacitance ? ? 7 pf guaranteed by characterization sid.xres#4 v hysxres input voltage hysteresis ? ? 0.05 v ddio mv guaranteed by characterization table 7. pwm ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid.tcpwm.3 t cpwmfreq operating frequency ? fc ? mhz fc max = clk_sys. maximum = 48 mhz. sid.tcpwm.4 t pwmenext input trigger pulse width ? 2/fc ? ns for all trigger events sid.tcpwm.5 t pwmext output trigger pulse width ? 2/fc ? ns minimum possible width of overflow, underflow, and cc (counter equals compare value) outputs sid.tcpwm.5a t cres resolution of counter ? 1/fc ? ns minimum time between successive counts sid.tcpwm.5b pwm res pwm resolution ? 1/fc ? ns minimum pulse width of pwm output sid.tcpwm.5c q res quadrature inputs resolution ? 1/fc ? ns minimum pulse width between quadrature-phase inputs
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 21 of 33 i 2 c table 8. fixed i 2 c dc specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid149 i i2c1 block current consumption at 100 kbps ? ? 60 a? sid150 i i2c2 block current consumption at 400 kbps ? ? 185 a? sid151 i i2c3 block current consumption at 1 mbps ? ? 390 a? sid152 i i2c4 i 2 c enabled in deep sleep mode ? ? 1.4 a? table 9. fixed i 2 c ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid153 f i2c1 bit rate ? ? 1 mbps ? table 10. fixed uart dc specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid160 i uart1 block current consumption at 100 kbps ? ? 125 a guaranteed by characterization sid161 i uart2 block current consumption at 1000 kbps ? ? 312 a guaranteed by characterization table 11. fixed uart ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid162 f uart bit rate ? ? 1 mbps guaranteed by characterization table 12. fixed spi dc specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid163 i spi1 block current consumption at 1 mbps ? ? 360 a guaranteed by characterization sid164 i spi2 block current consumption at 4 mbps ? ? 560 a guaranteed by characterization sid165 i spi3 block current consumption at 8 mbps ? ? 600 a guaranteed by characterization table 13. fixed spi ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid166 f spi spi operating frequency (master; 6x oversampling) ? ? 8 mhz guaranteed by characterization
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 22 of 33 memory table 14. fixed spi master mode ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid167 t dmo mosi valid after sclock driving edge ? ? 15 ns guaranteed by characterization sid168 t dsi miso valid before sclock capturing edge 20 ? ? ns full clock, late miso sampling. guaranteed by characterization sid169 t hmo previous mosi data hold time 0 ? ? ns referred to slave capturing edge. guaranteed by characterization table 15. fixed spi slave mode ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid170 t dmi mosi valid before sclock capturing edge 40 ? ? ns guaranteed by characterization sid171 t dso miso valid after sclock driving edge ? ? 42 + 3 * t cpu ns tcpu = 1/fcpu. guaranteed by characterization. sid171a t dso_ext miso valid after sclock driving edge in ext clk mode ? ? 48 ns guaranteed by characterization sid172 t hso previous miso data hold time 0 ? ? ns guaranteed by characterization sid172a t sselsck ssel valid to first sck valid edge 100 ? ? ns guaranteed by characterization table 16. flash ac specifications spec id parameter description min typ max units details/conditions sid.mem#4 t rowwrite [3] row (block) write time (erase and program) ? ? 20 ms row (block) = 128 bytes sid.mem#3 t rowerase [3] row erase time ? ? 13 ms ? sid.mem#8 t rowprogram [3] row program time after erase ? ? 7 ms ? sid178 t bulkerase [3] bulk erase time (32 kb) ? ? 35 ms ? sid180 t devprog [3] total device program time ? ? 7.5 seconds guaranteed by characterization sid181 f end flash endurance 100 k ? ? cycles guaranteed by characterization sid182 f ret1 flash retention. t a ? 55 c, 100 k p/e cycles 20 ? ? years guaranteed by characterization sid182a f ret2 flash retention. t a ? 85 c, 10 k p/e cycles 10 ? ? years guaranteed by characterization note 3. it can take as much as 20 milliseconds to write to flash. du ring this time the device should not be reset, or flash operation s will be interrupted and cannot be relied on to have completed. reset sources include the xres pin, softwa re resets, cpu lockup states and privilege violations, improper power supply levels, and watchdogs. make certain that these are not inadvertently activated.
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 23 of 33 system resources power-on-reset (por) with brown out swd interface internal main oscillator table 17. imprecise power on reset (pres) spec id parameter description min typ max units details/conditions sid185 v riseipor rising trip voltage 0.80 ? 1.50 v guaranteed by characterization sid186 v fallipor falling trip voltage 0.75 ? 1.4 v guaranteed by characterization table 18. precise power on reset (por) spec id parameter description min typ max units details/conditions sid190 v fallppor bod trip voltage in active and sleep modes 1.48 ? 1.62 v guaranteed by characterization sid192 v falldpslp bod trip voltage in deep sleep 1.1 ? 1.5 v guaranteed by characterization table 19. swd interface specifications spec id parameter description min typ max units details/conditions sid.swd#1 f_swdclk1 3.3 v ? v ddio ? 5.5 v ? ? 14 mhz swdclk 1/3 cpu clock frequency sid.swd#2 f_swdclk2 1.8 v ? v ddio ? 3.3 v ? ? 7 mhz swdclk 1/3 cpu clock frequency sid.swd#3 t_swdi_setup t = 1/f swdclk 0.25*t ? ? ns guaranteed by characterization sid.swd#4 t_swdi_hold t = 1/f swdclk 0.25*t ? ? ns guaranteed by characterization sid.swd#5 t_swdo_valid t = 1/f swdclk ? ? 0.5 * t ns guaranteed by characterization sid.swd#6 t_swdo_hold t = 1/f swdclk 1 ? ? ns guaranteed by characterization table 20. imo dc specifications (guaranteed by design) spec id parameter description min typ max units details/conditions sid218 i imo imo operating current at 48 mhz ? ? 1000 a? table 21. imo ac specifications spec id parameter description min typ max units details/conditions sid.clk#13 f imotol frequency variation at 24, 36, and 48 mhz (trimmed) ? ? 2 % ? sid226 t startimo imo startup time ? ? 7 s guaranteed by characterization sid229 t jitrmsimo rms jitter at 48 mhz ? 145 ? ps guaranteed by characterization f imo ? imo frequency 24 ? 48 mhz ?
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 24 of 33 internal low-speed oscillator power down table 22. ilo dc specifications (guaranteed by design) spec id parameter description min typ max units details/conditions sid231 i ilo ilo operating current at 32 khz ? 0.3 1.05 a guaranteed by characterization sid233 i iloleak ilo leakage current ? 2 15 na guaranteed by design table 23. ilo ac specifications spec id parameter description min typ max units details/conditions sid234 t startilo ilo startup time ? ? 2 ms guaranteed by characterization sid236 t iloduty ilo duty cycle 40 50 60 % guaranteed by characterization sid.clk#5 f ilo ilo frequency 20 40 80 khz ? table 24. pd dc specifications spec id parameter description min typ max units details/conditions sid.pd.1 rp_std dfp cc termination for default usb power 64 80 96 a ? sid.pd.2 rp_1.5a dfp cc termination for 1.5a power 166 180 194 a ? sid.pd.3 rp_3.0a dfp cc termination for 3.0a power 304 330 356 a ? sid.pd.4 rd ufp cc termination 4.59 5.1 5.61 k ? ? sid.pd.5 rd_db ufp dead battery cc termi- nation on rd1 and cc2 4.08 5.1 6.12 k ? all supplies forced to 0 v and 0.6 v applied at rd1 or cc2 sid.pd.6 r a power cable termination 0.8 1.0 1.2 k ? all supplies forced to 0 v and 0.2 v applied at v conn1 or v conn2 sid.pd.7 ra_off power cable termination - disabled 0.4 0.75 ? m ? 2.7 v applied at v conn1 or v conn2 with r a disabled sid.pd.8 rleak_1 v conn leaker for 0.1-f load ? ? 216 k ? managed active cable (mac) discharge sid.pd.9 rleak_2 v conn leaker for 0.5-f load ? ? 41.2 k ? sid.pd.10 rleak_3 v conn leaker for 1.0-f load ? ? 19.6 k ? sid.pd.11 rleak_4 v conn leaker for 2.0-f load ? ? 9.8 k ? sid.pd.12 rleak_5 v conn leaker for 5.0-f load ? ? 4.1 k ? sid.pd.13 rleak_6 v conn leaker for 10-f load ? ? 2.0 k ? sid.pd.14 ileak leaker on v conn1 and v conn2 for discharge upon cable detach 150 ? ? a ?
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 25 of 33 analog-to-digital converter table 25. adc dc specifications spec id parameter description min typ max units details/conditions sid.adc.1 resolution adc resolution ? 8 ? bits guaranteed by characterization sid.adc.2 inl integral non-linearity ?1.5 ? 1.5 lsb guaranteed by characterization sid.adc.3 dnl differential non-linearity ?2.5 ? 2.5 lsb guaranteed by characterization sid.adc.4 gain error gain error ?1 ? 1 lsb guaranteed by characterization table 26. adc ac specifications spec id parameter description min typ max units details/conditions sid.adc.5 slew_max rate of change of sampled voltage signal ? ? 3 v/ms guaranteed by characterization
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 26 of 33 ordering information the ez-pd ccg2 part numbers and features are listed in table 27 . ordering code definitions table 27. ez-pd ccg2 ordering information part number application type-c ports termination resistor role package CYPD2103-20FNXIT cable 1 r a [4] cable 20-ball csp cypd2103-14lhxit cable 1 r a [4] cable 14-pin dfn cypd2104-20fnxit accessory 1 r d [5] accessory 20-ball csp cypd2105-20fnxit active cable 1 r a [4] active cable 20-ball csp cypd2119-24lqxit c-dp 1 r d [5] ufp 24-pin qfn cypd2120-24lqxit c-hdmi 1 r d [5] ufp 24-pin qfn cypd2121-24lqxit dock/monitor upstream port 1 r p [6] , r d [5] drp 24-pin qfn cypd2122-20fnxit tablet 1 r p [6] , r d [5] drp 20-ball csp cypd2122-24lqxi notebook 1 r p [6] , r d [5] drp 24-pin qfn cypd2122-24lqxit notebook 1 r p [6] , r d [5] drp 24-pin qfn cypd2125-24lqxit dock/monitor downstream port 1 r p [6] dfp 24-pin qfn cypd2134-24lqxit dfp 1 r p [6] dfp 24-pin qfn cypd2134-24lqxqt dfp 1 r p [6] dfp 24-pin qfn t = tape and reel temperature grade: i = industrial ( ? 40 c to 85 c), q = extended industrial ( ? 40 c to105 c) pb-free package type: xx = fn, lh or lq fn = csp; lh = dfn; lq = qfn number of pins in the package: xx = 14, 20, or 24 device role: unique combination of role and termination: x = 0 or 1 or 2 or 3 or 4 or 5 or 9 feature: unique applications: x = 0 or 1 or 2 or 3 number of type-c ports: 1 = 1 port product type: 2 = second-generation product family, ccg2 marketing code: pd = power delivery product family company id: cy = cypress cy xx pd 2 1 x xx - i x x t notes 4. termination resistor denoting an emca. 5. termination resistor denoting an accessory or upstream facing port. 6. termination resistor denoting a downstream facing port.
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 27 of 33 packaging figure 15. 20-ball wlcsp (1.63 ? 2.03 0.55 mm) fn20b package outline, 001-95010 table 28. package characteristics parameter description conditions min typ max units t a operating ambient temperature industrial ?40 25 85 c extended industrial 105 c t j operating junction temperature industrial ?40 ? 100 c extended industrial 125 c t ja package ? ja (20-ball wlcsp) ? ? 66 ? c/w t jc package ? jc (20-ball wlcsp) ? ? 0.7 ? c/w t ja package ? ja (14-pin dfn) ? ? 31 ? c/w t jc package ? jc (14-pin dfn) ? ? 59 ? c/w t ja package ? ja (24-pin qfn) ? ? 22 ? c/w t jc package ? jc (24-pin qfn) ? ? 29 ? c/w table 29. solder reflow peak temperature package maximum peak temperature maximum time within 5 c of peak temperature 20-ball wlcsp 260 c 30 seconds 14-pin dfn 260 c 30 seconds 24-pin qfn 260 c 30 seconds table 30. package moisture sensitivity level (msl), ipc/jedec j-std-2 package msl 20-ball wlcsp msl 1 14-pin dfn msl 3 24-pin qfn msl 3 top view bottom view side view notes: 1. reference jedec publication 95, design guide 4.18 2. all dimensions are in millimeters 4 3 2 1 e d c b a 4 3 2 1 e d c b a 001-95010 *a
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 28 of 33 figure 16. 14-pin dfn (2.5 3.5 0.6 mm), lh14a, 0.95 3.00 e-pad (sawn) package outline, 001-96312 figure 17. 24-pin qfn (4 4 0.55 mm), lq24a, 2.65 2.65 e-pad (sawn) package outline, 001-13937 001-96312 ** 001-13937 *f
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 29 of 33 acronyms table 31. acronyms used in this document acronym description adc analog-to-digital converter api application programming interface arm ? advanced risc machine, a cpu architecture cc configuration channel ccg2 cable controller generation 2 cpu central processing unit crc cyclic redundancy check, an error-checking protocol cs current sense dfp downstream facing port dio digital input/output, gpio with only digital capabil- ities, no analog. see gpio. drp dual role port eeprom electrically erasable programmable read-only memory emca a usb cable that includes an ic that reports cable characteristics (e.g., curren t rating) to the type-c ports emi electromagnetic interference esd electrostatic discharge fpb flash patch and breakpoint fs full-speed gpio general-purpose input/output ic integrated circuit ide integrated deve lopment environment i 2 c, or iic inter-integrated circuit, a communications protocol ilo internal low-speed oscillator, see also imo imo internal main oscillator, see also ilo i/o input/output, see also gpio lvd low-voltage detect lvttl low-voltage transistor-transistor logic mcu microcontroller unit nc no connect nmi nonmaskable interrupt nvic nested vectored interrupt controller opamp operational amplifier ocp overcurrent protection ovp overvoltage protection pcb printed circuit board pd power delivery pga programmable gain amplifier phy physical layer por power-on reset pres precise power-on reset psoc ? programmable system-on-chip? pwm pulse-width modulator ram random-access memory risc reduced-instruction-set computing rms root-mean-square rtc real-time clock rx receive sar successive approxi mation register scl i 2 c serial clock sda i 2 c serial data s/h sample and hold spi serial peripheral interface, a communications protocol sram static random access memory swd serial wire debug, a test protocol tx transmit type-c a new standard with a slimmer usb connector and a reversible cable, capable of sourcing up to 100 w of power uart universal asynchronous transmitter receiver, a communications protocol usb universal serial bus usbio usb input/output, ccg2 pins used to connect to a usb port xres external reset i/o pin table 31. acronyms us ed in this document (continued) acronym description
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 30 of 33 document conventions units of measure table 32. units of measure symbol unit of measure c degrees celsius hz hertz kb 1024 bytes khz kilohertz k ? kilo ohm mbps megabits per second mhz megahertz m ? mega-ohm msps megasamples per second a microampere f microfarad s microsecond v microvolt w microwatt ma milliampere ms millisecond mv millivolt na nanoampere ns nanosecond ? ohm pf picofarad ppm parts per million ps picosecond ssecond sps samples per second vvolt table 32. units of measure (continued) symbol unit of measure
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 31 of 33 references and links to applications collaterals knowledge base articles key differences among ez-pd? ccg1, ccg2, ccg3 and ccg4 - kba210740 programming ez-pd? ccg2, ez-pd? ccg3 and ez-pd? ccg4 using psoc? programmer and miniprog3 - kba96477 ccgx frequently asked questions (faqs) - kba97244 handling precautions for cy4501 ccg1 dvk - kba210560 cypress ez-pd? ccgx hardware - kba204102 difference between usb type-c and usb-pd - kba204033 ccgx programming methods - kba97271 getting started with cypress usb type-c products - kba04071 type-c to displayport cable electrical requirements dead battery charging implementation in usb type-c solutions - kba97273 termination resistors required for the usb type-c connector ? kba97180 vbus bypass capacitor recommendation for type-c cable and type-c to legacy cable/adapter assemblies ? kba97270 need for regulator and auxiliary switch in type-c to displayport (dp) cable solution - kba97274 need for a usb billboard device in type-c solutions ? kba97146 ccg1 devices in type-c to leg acy cable/adapte r assemblies ? kba97145 cypress usb type-c controller supported solutions ? kba97179 termination resistors for type -c to legacy ports ? kba97272 handling instructions for cy4502 ccg2 development kit ? kba97916 thunderbolt? cable application using ccg3 devices - kba210976 power adapter application using ccg3 devices - kba210975 methods to upgrade firmware on ccg3 devices - kba210974 device flash memory size and advantages - kba210973 applications of ez-pd? ccg4 - kba210739 application notes an96527 - designing usb type-c products using cypress?s ccg1 controllers an95615 - designing usb 3.1 type-c cables using ez-pd? ccg2 an95599 - hardware design guidelines for ez-pd? ccg2 an210403 - hardware design guidelines for dual role port applications using ez-pd? usb type-c controllers an210771 - getting started with ez-pd? ccg4 reference designs ez-pd? ccg2 electronically marked cable assembly (emca) paddle card reference design ez-pd? ccg2 usb type-c to displayport cable solution ccg1 usb type-c to displayport cable solution ccg1 usb type-c to hdmi/dvi/vga adapter solution ez-pd? ccg2 usb type-c to hdmi adapter solution ccg1 electronically marked cable assembly (emca) paddle card reference design ccg1 usb type-c to legacy usb device cable paddle card reference schematics ez-usb gx3 usb type-c to gigabit ethernet dongle ez-pd? ccg2 usb type-c monitor/dock solution ccg2 20w power adapter reference design ccg2 18w power adapter reference design ez-usb gx3 usb type-a to gigabit ethernet reference design kit kits cy4501 ccg1 development kit cy4502 ez-pd? ccg2 development kit cy4531 ez-pd ccg3 evaluation kit cy4541 ez-pd? ccg4 evaluation kit datasheets ccg1 datasheet: usb type-c port controller with power delivery cypd1120 datasheet: usb po wer delivery alternate mode controller on type-c ccg3: usb type-c controller datasheet ccg4: two-port usb type-c controller datasheet
ez-pd? ccg2 datasheet document number: 001-93912 rev. *l page 32 of 33 document history page description title: ez-pd? ccg2 dat asheet usb type-c port controller document number: 001-93912 revision ecn orig. of change submission date description of change *e 4680071 gaya 03/07/2015 release to web *f 4718374 akn 04/09/2015 added 24-pin qfn pin and package information. added drp and dfp application diagrams *g 4774142 akn 06/15/2015 changed datasheet status from preliminary to final. updated logic block diagram. changed number of gpios to 10 and add ed a note about the number of gpios varying depending on the package. updated power and digital peripherals section. updated application diagrams. added sid.pwr#1_a parameter. added cypd2122-20fnxit part in ordering information. removed errata. *h 4979175 vgt 10/23/2015 updated figure 1 and figure 5. added vcc_abs spec and updated the sid.adc.4 parameter. added ?guaranteed by characterization? note for the following specs: sid.gio#16, sid.gi o#17, sid.xres#3, sid 160 to sid 172a, sid 2226, sid 229, sid.adc.1 to sid.adc.5. *i 5028128 vgt 12/04/2015 updated application diagrams : added figure 12 . added figure 13 . added figure 14 . updated ordering information . added part numbers cypd2119-24lqxit, cypd2120-24lqxit, cypd2121-24lqxit, cypd2125-24lqxit. *j 5186972 vgt 03/28/2016 updated temperature ranges in features . updated ta b l e 2 8 . updated ordering information . *k 5303957 vgt 06/13/2016 added available firmware and software tools . updated figure 8 : per the usb pd3.0 spec, sop? implementation is no longer valid for passive cables. updated figure 9 , figure 10 , and figure 11 . added descriptive notes for the application diagrams. added references and links to applications collaterals . updated ordering information . updated cypress logo and copyright information. *l 5387677 vgt 08/02/2016 added cypd2122-24lqxi part number in ordering information .
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